Performed at the wafer sort level in production, an IDDQ test is a method for detecting the presence of manufacturing faults in CMOS integrated circuits. The IDDQ test measures the quiescent leakage current of dies at a logic state in order to determine whether potentially malfunctioning circuitry exist in an integrated circuit device. Such a defective circuit may operate properly at a time of the test. However, due to reliability defects, it may cause a premature malfunction of the integrated circuit device.
A typical IDDQ test is implemented by taking a multitude of current measurements, covering approximately 95% of logic states of an integrated circuit device. Due to the number of testes, IDDQ current measurement processes can take a considerable amount of time. It is within this context that the present invention arises.